Apéndices
Escrito el Lunes 06 de Abril del 2009 por Ealdor
[A] Instruction addressing modes and related execution times
A A
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A Z Z t A Z Z t
c e r A A (I (I e c e r A A (I (I e
c I Z r r b b n n c I Z r r b b n n
u m e o o A s s R d d I u m e o o A s s R d d I
m m r b o o I e i i n m m r b o o I e i i n
u e o P P s l l m l r r d u e o P P s l l m l r r d
l d a a o u u p a e e i l d a a o u u p a e e i
a i P g g l t t l t c c r a i P g g l t t l t c c r
t a a e e u e e i i t, t) e t a a e e u e e i i t, t) e
o t g t e v c o t g t e v c
r e e X Y e X Y d e X) ,Y t r e e X Y e X Y d e X) ,Y t
ADC . 2 3 4 . 4 4* 4* . . 6 5* 6 JSR . . . . . 6 . . . . . . .
AND . 2 3 4 . 4 4* 4* . . 6 5* LDA . 2 3 4 . 4 4* 4* . . 6 5* .
ASL 2 . 5 6 . 6 7 . . . . . . LDX . 2 3 . 4 4 . 4* . . . . .
BCC . . . . . . . . . 2**. . . LDY . 2 3 4 . 4 4* . . . . . .
BCS . . . . . . . . . 2**. . . LSR 2 5 6 . 6 7 . . . . . . .
BEQ . . . . . . . . . 2**. . . NOP . . . . . . . . 2 . . . .
BIT . . 3 . . 4 . . . . . . . ORA . 2 3 4 . 4 4* 4* . . 6 5* .
BMI . . . . . . . . . 2**. . . PHA . . . . . . . . 3 . . . .
BNE . . . . . . . . . 2**. . . PHP . . . . . . . . 3 . . . .
BPL . . . . . . . . . 2**. . . PLA . . . . . . . . 4 . . . .
BRK . . . . . . . . . . . . . PLP . . . . . . . . 4 . . . .
BVC . . . . . . . . . 2**. . . ROL 2 . 5 6 . 6 7 . . . . . .
BVS . . . . . . . . . 2**. . . ROR 2 . 5 6 . 6 7 . . . . . .
CLC . . . . . . . . 2 . . . . RTI . . . . . . . . 6 . . . .
CLD . . . . . . . . 2 . . . . RTS . . . . . . . . 6 . . . .
CLI . . . . . . . . 2 . . . . SBC . 2 3 4 . 4 4* 4* . . 6 5* .
EOR . 2 3 4 . 4 4* 4* . . 6 5 . TAY . . . . . . . . 2 . . . .
INC . . 5 6 . 6 7 . . . . . . TSX . . . . . . . . 2 . . . .
INX . . . . . . . . 2 . . . . TXA . . . . . . . . 2 . . . .
INY . . . . . . . . 2 . . . . TXS . . . . . . . . 2 . . . .
JMP . . . . . 3 . . . . . . 5 TYA . . . . . . . . 2 . . . .
* Add one cycle if indexing across page boundary
** Add one cycle if branch taken, Add one additional if branching operation crosses page boundary
[B] Operation instruction listing hexadecimal sequence
00 - BRK 20 - JSR 01 - ORA - (Indirect,X) 21 - AND - (Indirect,X) 02 - Future Expansion 22 - Future Expansion 03 - Future Expansion 23 - Future Expansion 04 - Future Expansion 24 - BIT - Zero Page 05 - ORA - Zero Page 25 - AND - Zero Page 06 - ASL - Zero Page 26 - ROL - Zero Page 07 - Future Expansion 27 - Future Expansion 08 - PHP 28 - PLP 09 - OPA - Immediate 29 - AND - Immediate 0A - ASL - Accumulator 2A - ROL - Accumulator 0B - Future 2B - Future Expansion 0C - Future Expansion 2C - BIT - Absolute 0D - OPA - Absolute 2D - AND - Absolute 0E - ASL - Absolute 2E - ROL - Absolute 0F - Future Expansion 2F - Future Expansion 10 - BPL 30 - BMI 11 - OPA - (Indirect),Y 31 - AND - (Indirect),Y 12 - Future Expansion 32 - Future Expansion 13 - Future Expansion 33 - Future Expansion 14 - Future Expansion 34 - Future Expansion 15 - ORA - Zero Page,X 35 - AND - Zero Page,X 16 - ASL - Zero Page,X 36 - ROL - Zero Page,X 17 - Future Expansion 37 - Future Expansion 18 - CLC 38 - SEC 19 - ORA - Absolute,Y 39 - AND - Absolute,Y 1A - Future Expansion 3A - Future Expansion 1B - Future Expansion 3B - Future Expansion 1C - Future Expansion 3C - Future Expansion 1D - ORA - Absolute,X 3D - AND - Absolute,X 1E - ASL - Absolute,X 3E - ROL - Absolute,X 1F - Future Expansion 3F - Future Expansion 40 - RTI 60 - RTS 41 - EOR - (Indirect,X) 61 - ADC - (Indirect,X) 42 - Future Expansion 62 - Future Expansion 43 - Future Expansion 63 - Future Expansion 44 - Future Expansion 64 - Future Expansion 45 - EOR - Zero Page 65 - ADC - Zero Page 46 - LSR - Zero Page 66 - ROR - Zero Page 47 - Future Expansion 67 - Future Expansion 48 - PHA 68 - PIA 49 - EOR - Immediate 69 - ADC - Immediate 4A - LSR - Accumulator 6A - ROR - Accumulator 4B - Future Expansion 68 - Future Expansion 4C - JMP - Absolute 6C - JMP - Indirect 4D - EOR - Absolute 6D - ADC - Absolute 4E - LSR - Absolute 6E - ROR - Absolute 4F - Future Expansion 6F - Future Expansion 50 - BVC 70 - BVS 51 - EOR - (Indirect),Y 71 - ADC - (Indirect),Y 52 - Future Expansion 72 - Future Expansion 53 - Future Expansion 73 - Future Expansion 54 - Future Expansion 74 - Future Expansion 55 - EOR - Zero Page,X 75 - ADC - Zero Page,X 56 - LSR - Zero Page,X 76 - ROR - Zero Page,X 57 - Future Expansion 77 - Future Expansion 58 - CLI 78 - SEI 59 - EOR - Absolute,Y 79 - ADC - Absolute,Y 5A - Future Expansion 7A - Future Expansion 5B - Future Expansion 78 - Future Expansion 5C - Future Expansion 7C - Future Expansion 5D - EOR - Absolute,X 7D - ADC - Absolute,X 5E - LSR - Absolute,X 7E - ROR - Absolute,X 5F - Future Expansion 7F - Future Expansion 80 - Future Expansion A0 - LDY - Immediate 81 - STA - (Indirect,X) A1 - LDA - (Indirect,X) 82 - Future Expansion A2 - LDX - Immediate 83 - Future Expansion A3 - Future Expansion 84 - STY - Zero Page A4 - LDY - Zero Page 85 - STA - Zero Page A5 - LDA - Zero Page 86 - STX - Zero Page A6 - LDX - Zero Page 87 - Future Expansion A7 - Future Expansion 88 - DEY A8 - TAY 89 - Future Expansion A9 - LDA - Immediate 8A - TXA A0 - TAX 8B - Future Expansion AD - Future Expansion 8C - STY - Absolute AC - LDY - Absolute 8D - STA - Absolute AD - LDA - Absolute 8E - STX - Absolute AE - LDX - Absolute 8F - Future Expansion AF - Future Expansion 98 - BCC B0 - BCS 91 - STA - (Indirect),Y B1 - LDA - (Indirect),Y 92 - Future Expansion B2 - Future Expansion 93 - Future Expansion B3 - Future Expansion 94 - STY - Zero Page,X B4 - LDY - Zero Page,X 95 - STA - Zero Page,X B5 - LDA - Zero Page,X 96 - STX - Zero Page,Y B6 - LDX - Zero Page,Y 97 - Future Expansion B7 - Future Expansion 98 - TYA B8 - CLV 99 - STA - Absolute,Y B9 - LDA - Absolute,Y 9A - TXS BA - TSX 98 - Future Expansion BB - Future Expansion 9C - Future Expansion BC - LDY - Absolute,X 9D - STA - Absolute,X BD - LDA - Absolute,X 9E - Future Expansion BE - LDX - Absolute,Y 9F - Future Expansion BF - Future Expansion C0 - CPY - Immediate E0 - CPX - Immediate C1 - CMP - (Indirect,X) E1 - SBC - (Indirect,X) C2 - Future Expansion E2 - Future Expansion C3 - Future Expansion E3 - Future Expansion C4 - CPY - Zero Page E4 - CPX - Zero Page C5 - CMP - Zero Page E5 - SBC - Zero Page C6 - DEC - Zero Page E6 - INC - Zero Page C7 - Future Expansion E7 - Future Expansion CS - INY E5 - INX C9 - CMP - Immediate E9 - SBC - Immediate CA - DEX EA - NOP CB - Future Expansion EB - Future Expansion CC - CPY - Absolute EC - CPX - Absolute CD - CMP - Absolute ED - SBC - Absolute CE - DEC - Absolute EE - INC - Absolute CF - Future Expansion EF - Future Expansion D0 - BNE F0 - BEQ D1 - CMP - (Indirect),Y F1 - SBC - (Indirect),Y D2 - Future Expansion F2 - Future Expansion D3 - Future Expansion F3 - Future Expansion D4 - Future Expansion F4 - Future Expansion D5 - CMP - Zero Page,X F5 - SBC - Zero Page,X D6 - DEC - Zero Page,X F6 - INC - Zero Page,X D7 - Future Expansion F7 - Future Expansion D8 - CLD F8 - SED D9 - CMP - Absolute,Y F9 - SBC - Absolute,Y DA - Future Expansion FA - Future Expansion DB - Future Expansion FB - Future Expansion DC - Future Expansion FC - Future Expansion DD - CMP - Absolute,X FD - SBC - Absolute,X DE - DEC - Absolute,X FE - INC - Absolute,X DF - Future Expansion FF - Future Expansion
[C] Summary of adressing modes
This appendix is to serve the user in providing a reference for the MCS650X addressing modes. Each mode of address is shown with a symbolic illustration of the bus Status at each cycle during the instruction fetch and execution. The example number as found in the text is provided for reference purposes.
E.1 IMPLIED ADDRESSING: Clock Cycle Address Bus Program Counter Data Bus Comments 1 PC PC + 1 OP CODE Fetch OP CODE 2 PC + 1 PC + I New OP CODE Ignore New OP CODE; Decode Old OP CODE 3 PC + 1 PC + 2 New OP CODE Fetch New OP CODE; Execute Old OP CODE E. 2 IMMEDIATE ADDRESSING: Clock Cycle Address Bus Program Counter Data Bus Comments 1 PC PC + 1 OP CODE Fetch OP CODE 2 PC + 1 PC + 2 Data Fetch Data, Decode OP CODE 3 PC + 2 PC + 3 New OP CODE Fetch New OP CODE, Execute Old OP CODE E.3 ABSOLUTE ADDRESSING: Clock Cycle Address Bus Program Counter Data Bus Comments 1 PC PC + 1 OP CODE Fetch OP CODE 2 PC + 1 PC + 2 ADL Fetch AOL, Decode OP CODE 3 PC + 2 PC + 3 ADH Fetch AOH, Retail AOL 4 AOH, AOL PC + 3 Data Fetch Data 5 PC + 3 PC + 4 New OP CODE Fetch New OP CODE, Execute Old OP CODE E.4 ZERO PAGE ADDRESSING: Clock Cycle Address Bus Program Counter Data Bus Comments 1 PC PC + 1 OP CODE Fetch OP CODE 2 PC + 1 PC + 2 ADL Fetch ADL, Decode OP CODE 3 00, AOL PC + 2 Data Fetch Data 4 PC + 2 PC + 3 New OP CODE Fetch New OP CODE, Execute Old OP CODE E.5 RELATIVE ADDRESSING - (Branch Positive, no crossing of page boundaries): Cycle Address Bus Data Bus External Operation Internal Operation 1 0100 OP CODE Fetch OP CODE Finish Previous Operation, Increment Program Counter to 101 2 0101 +50 Fetch Offset Interpret Instruction, Increment Program Counter to 102 3 0102 Next OP CODE Fetch Next OP CODE Check Flags, Add Relative to PCL, Increment Program Counter to 103 4 0152 Next OP CODE Fetch Next OP CODE Transfer Results to PCL, Increment Program Counter to 153 E.6 ABSOLUTE INDEXED ADDRESSING - (with page crossing) Step 5 is deleted and the data in step 4 is valid when no page crossing occurs: Cycle Address Bus Data Bus External Operation InternalOperation 1 0100 OP CODE Fetch OP CODE Finish Previous Operation Increment PC to 101 2 0101 BAL Fetch BAL Interpret Instruction Increment PC to 102 3 0102 BAB Fetch BAH Add BAL + Index Increment PC to 103 4 BAH,BAL +X Data (Ignore) Fetch Data (Data is ignored) Add BAH + Carry 5 BAH+1, BAL+X Data Fetch Data 6 0103 Next OP CODE Fetch Next OP CODE Finish Operation E.7 ZERO PAGE INDEXED ADDRESSING: Cycle Address Bus Data Bus External Operation Internal Operation 1 0100 OP CODE Fetch OP CODE Finish Previous Operation 2 0101 BAL Fetch Base Address Low (BAL) Interpret Instruction 3 D0,BAL Data (Discarded) Fetch Discarded Data Add: BAL + X 4 00,BAL Data Fetch Data 5 0102 Next OP CODE Fetch Next OP CODE Finish Operation E.8 INDEXED INDIRECT ADDRESSING: Cycle Address Bus Data Bus External Operation Internal Operation 1 0100 OP CODE Fetch OP CODE Finish Previous Operation 2 0101 BAL Fetch BAL Interpret Instruction 3 00,BAL DATA (Discarded) Fetch Discarded DATA Add BAL + X 4 00,BAL AOL Fetch ADL Add 1 to BAL + X 5 00,BAL + x + l Fetch ADH Hold ADL 6 ADH,ADL DATA Fetch DATA 7 0102 Next OP Fetch Next OP CODE Finish Operation E.9 INDIRECT IVDEXED ADDRESSING (with page crossing) Step 6 is deleted and the data in step 5 is valid when no page crossing occurs: Cycle Address Bus Data Bus External Operation Internal Operation 1 0100 OP CODE Load OP CODE Finish Previous Operation 2 0101 IAL Fetch IAL Interpret Instruction 3 00,IAL BAL Fetch BAL Add 1 to IAL 4 00,IAL BAH + 1 Fetch BAH Add BAL to Y 5 BAH,BAL + Y DATA(Discarded) Fetch DATA (Discarded) Add 1 to BAH 6 BAH + 1, BAL + Y DATA Fetch Data 7 0102 Next OP CODE Fetch Next OP CODE Finish This Operation
[D] MCS650X programming model
